More Information

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Information Subject
Your first and last name
Title
Company
Department
Email
City
State
Zip
Country
Phone number
What is your job function? System Architect
RTL Logic Design
Logic Design Verification
Firmware Engineering
Methodology or CAD
Marketing / Business Dev
Foundry
IP provider
Engineering Management
Corporate Management
Other:
What are your typical design sizes where RTL simulation is too slow? Less than 50k gates
Between 50k gates and 250k gates
Between 250k gates and 1M gates
Between 1M gates and 2M gates
Between 2M gates and 4M gates
Above 4M gates
What is your typical RTL simulation run-time? Less than 30 minutes
Between 30 minutes and 1 hour
Between 1 hour and 2 hours
Between 2 hours and 5 hours
Between 5 hours and 10 hours
About a day
Several days
More than a week